The present invention relates, in general, to the field of multi-processor based computer systems. More particularly, the present invention relates to a multi-processor computer architecture incorporating distributed multi-ported common memory (MPCM) modules, each comprising a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices.
In computer systems it is often desirable to allow multiple processors to have access to a single, large shared common memory. Historically, this has necessitated a physically large assembly in order to reach memory capacity in excess of 1 TByte. Some conventional systems attempt to decrease the physical size of the memory by distributing it among numerous processor boards and then employing one of several software protocols, such as the Message Passing Interface (MPI), to allow all of the processors to access all of the memory. The problem with such methodologies is that they exhibit very high memory access latencies and consume significant processing power just to effectuate sharing of the data.
The foregoing approach is not in line with the current market trends toward low processing power microprocessors situated on small physical footprint circuit boards to enable very dense packaging.